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DATA SHEET
256MB Unbuffered SDRAM DIMM
HB52F328EM-75B (32M words x 64 bits, 1 bank) HB52F329EM-75B (32M words x 72 bits, 1 bank)
Description
The HB52F328EM and HB52F329EM belong to 8-byte DIMM (Dual In-line Memory Module) family, and have been developed as an optimized main memory solution for 8-byte processor applications. They are synchronous Dynamic RAM Module, mounted 256M bits SDRAMs (HM5225805BTT) sealed in TSOP package, and 1 piece of serial EEPROM (2k bits) for Presence Detect (PD). The HB52F328EM is organized 32M x 64 x 1 bank mounted 8 pieces of 256M bits SDRAM. The HB52F329EM is organized 32M x 72 x 1 bank mounted 9 pieces of 256M bits SDRAM. Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board. * 2 variations of refresh Auto refresh Self refresh
Features
* Fully compatible with: JEDEC standard outline 8byte DIMM * 168-pin socket type package (dual lead out) Outline: 133.37mm (Length) x 34.925mm (Height) x 4.00mm (Thickness) Lead pitch: 1.27mm * 3.3V power supply * Clock frequency: 133MHz (max.) * LVTTL interface * Data bus width : x 64 Non parity (HB52F328EM) : x 72 ECC (HB52F329EM) * Single pulsed /RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length (BL): 1, 2, 4, 8 * 2 variations of burst sequence Sequential Interleave * Programmable /CE latency (CL) : 3 (133MHz) : 2 (100MHz) * Byte control by DQMB * Refresh cycles: 8192 refresh cycles/64ms
Document No. E0184H10 (Ver. 1.0) Date Published June 2001 Printed in Japan URL: http://www.elpida.com
C
Elpida Memory, Inc. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52F328EM-75B, HB52F329EM-75B
Ordering Information
Part number HB52F328EM-75B* HB52F329EM-75B* Clock frequency MHz (max.) 133 133 /CE latency 3 3 Package 168-pin dual lead out socket type Contact pad Gold
Note: 100MHz operation at /CE latency = 2.
Pin Configurations
1 pin 10 pin 11 pin 40 pin 41 pin 84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
[HB52F328EM]
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC NC VSS NC NC VCC /W DQMB0 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Pin name VSS NC /S2 DQMB2 DQMB3 NC VCC NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC NC VSS NC NC VCC /CE DQMB4 Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 Pin name VSS CKE0 NC DQMB6 DQMB7 NC VCC NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57
Data Sheet E0184H10 (Ver. 1.0)
2
HB52F328EM-75B, HB52F329EM-75B
Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name DQMB1 /S0 NC VSS A0 A2 A4 A6 A8 A10 (AP) BA1 VCC VCC CK0 Pin No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin name DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VCC Pin No. 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin name DQMB5 NC /RE VSS A1 A3 A5 A7 A9 BA0 A11 VCC CK1 A12 Pin No. 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin name DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VCC
[HB52F329EM]
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pin name VSS NC /S2 DQMB2 DQMB3 NC VCC NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 Pin name VSS CKE0 NC DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS
Data Sheet E0184H10 (Ver. 1.0)
3
HB52F328EM-75B, HB52F329EM-75B
Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name /W DQMB0 DQMB1 /S0 NC VSS A0 A2 A4 A6 A8 A10 (AP) BA1 VCC VCC CK0 Pin No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin name DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VCC Pin No. 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin name /CE DQMB4 DQMB5 NC /RE VSS A1 A3 A5 A7 A9 BA0 A11 VCC CK1 A12 Pin No. 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin name DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VCC
Pin Description
[HB52F328EM]
Pin name A0 to A12 Function Address input Row address A0 to A12 Column address A0 to A9 Bank select address Data input/output Chip select input Row enable (/RAS) input Column enable (/CAS) input Write enable input Byte data mask Clock input Clock enable input Write protect for serial PD Data input/output for serial PD Clock input for serial PD Serial address input Primary positive power supply Ground No connection
BA0, BA1 DQ0 to DQ63 /S0, /S2 /RE /CE /W DQMB0 to DQMB7 CK0, CK2 CKE0 WP SDA SCL SA0 to SA2 VCC VSS NC
Data Sheet E0184H10 (Ver. 1.0)
4
HB52F328EM-75B, HB52F329EM-75B
[HB52F329EM]
Pin name A0 to A12 Function Address input Row address A0 to A12 Column address A0 to A9 Bank select address Data input/output Check bit (Data input/output) Chip select input Row enable (/RAS) input Column enable (/CAS) input Write enable input Byte data mask Clock input Clock enable input Write protect for serial PD Data input/output for serial PD Clock input for serial PD Serial address input Primary positive power supply Ground No connection
BA0, BA1 DQ0 to DQ63 CB0 to CB7 /S0, /S2 /RE /CE /W DQMB0 to DQMB7 CK0, CK2 CKE0 WP SDA SCL SA0 to SA2 VCC VSS NC
Data Sheet E0184H10 (Ver. 1.0)
5
HB52F328EM-75B, HB52F329EM-75B
Serial PD Matrix*
Byte No. 0 1 2 3 4 5 6
1
Function described Number of bytes used by module manufacturer Total SPD memory size Memory type Number of row addresses bits Number of column addresses bits Number of banks Module data width (HB52F328EM) (HB52F329EM)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 80 08 04 0D 0A 01 40 48 00 01 75
Comments 128 256 byte SDRAM 13 10 1 64 bit 72 bit 0 (+) LVTTL CL = 3
7 8 9
Module data width (continued) Module interface signal levels SDRAM cycle time (highest /CE latency) 7.5ns SDRAM access from Clock (highest /CE latency) 5.4ns Module configuration type (HB52F328EM) (HB52F329EM)
10 11
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0
1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0
0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 0
0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0
54 00 02 82 08 00 08 01 0F 04 06 01 01 00 0E A0 Non parity ECC Normal (7.8125 s) Self refresh 32M x 8 -- x8 1 CLK 1, 2, 4, 8 4 2, 3 0 0 Non buffer VCC 10% CL = 2
12 13 14
Refresh rate/type SDRAM width Error checking SDRAM width (HB52F328EM) (HB52F329EM) SDRAM device attributes: minimum clock delay for back-toback random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: /CE latency SDRAM device attributes: /S latency SDRAM device attributes: /W latency SDRAM device attributes SDRAM device attributes: General SDRAM cycle time (2nd highest /CE latency) 10ns SDRAM access from Clock (2nd highest /CE latency) 6ns SDRAM cycle time (3rd highest /CE latency) Undefined
15 16 17 18 19 20 21 22 23
24
0
1
1
0
0
0
0
0
60
25
0
0
0
0
0
0
0
0
00
Data Sheet E0184H10 (Ver. 1.0)
6
HB52F328EM-75B, HB52F329EM-75B
Byte No. 26 27 28 29 30 31 32 33 34 35 36 to 61 62 63 Function described SDRAM access from Clock (3rd highest /CE latency) Undefined Minimum row precharge time Row active to row active min /RE to /CE delay min Minimum /RE pulse width Density of each bank on module Address and command signal input setup time Address and command signal input hold time Data signal input setup time Data signal input hold time Superset information SPD data revision code Checksum for bytes 0 to 62 (HB52F328EM)) (HB52F329EM) 64 65 to 71 72 73 74 75 76 77 78 79 80 Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part (HB52F328EM) (HB52F329EM) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Revision code Revision code Manufacturing date Manufacturing date Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 x 1 1 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 x x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 x 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 x x 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 0 x 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 0 x x 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 x 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 x x 0 1 1 1 1 0 1 0 1 0 0 0 0 1 1 0 x 0 0 1 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 x x 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 x 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 x x 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 x 0 0 1 0 0 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 x x 00 14 0F 14 2D 40 15 08 15 08 00 02 42 54 07 00 xx 48 42 35 32 46 33 32 38 39 45 4D 2D 37 35 42 20 20 20 20 30 20 xx xx *2 (ASCII-8bit code) H B 5 2 F 3 2 8 9 E M -- 7 5 B (Space) (Space) (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD) 20ns 15ns 20ns 45ns 1 bank 256M byte 1.5ns 0.8ns 1.5ns 0.8ns Future use JEDEC2 66 84 HITACHI Comments
Data Sheet E0184H10 (Ver. 1.0)
7
HB52F328EM-75B, HB52F329EM-75B
Byte No. 95 to 98 99 to 125 126 127 Function described Assembly serial number Manufacturer specific data Reserved (Intel specification frequency) Reserved (Intel specification /CE# latency support) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value *
3
Comments
-- 0 1
-- 1 0
-- 1 1
-- 0 0
-- 0 1
-- 1 1
-- 0 1
-- 0 1
-- 64 AF
*4
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High". 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 125 are not defined ("1" or "0").
Data Sheet E0184H10 (Ver. 1.0)
8
HB52F328EM-75B, HB52F329EM-75B
Block Diagram (HB52F328EM)
A0 to A12, BA0, BA1 /RE, /CE, /W /S0 /CS DQMB0 8 DQ0 to DQ7 10 DQM I/O0 to I/O7 /CS DQM 8 DQ8 to DQ15 10 I/O0 to I/O7 /CS
D0
DQMB4 8 DQ32 to DQ39 10
DQM I/O0 to I/O7 /CS DQM 8 10 I/O0 to I/O7
D4
DQMB1
D1
DQMB5 DQ40 to DQ47
D5
/S2 /CS DQMB2 8 DQ16 to DQ23 10 DQM I/O0 to I/O7 /CS DQM 8 DQ24 to DQ31 10 I/O0 to I/O7 /CS
D2
DQMB6 8 DQ48 to DQ55 10
DQM I/O0 to I/O7 /CS DQM 8 10 I/O0 to I/O7
D6
DQMB3
D3
DQMB7 DQ56 to DQ63
D7
10 CK0 10 CK2
VCC 0.33F CLK x 8 pcs :4 SDRAMs + 3.3pF cap VSS
VCC (D0 to D7, U0)
0.1F x 8 pcs
VSS (D0 to D7, U0)
CLK :4 SDRAMs + 3.3pF cap SCL 10
Serial PD SCL SDA SDA
CK1, CK3 10pF A0
U0
A1 A2 WP 47k
CKE0
CKE (D0 to D7)
SA0 SA1 SA2
VSS
Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D7: HM5225805 U0: 2k bits EEPROM
Data Sheet E0184H10 (Ver. 1.0)
9
HB52F328EM-75B, HB52F329EM-75B
Block Diagram (HB52F329EM)
A0 to A12, BA0, BA1 /RE, /CE, /W /S0 /CS DQMB0 8 DQ0 to DQ7 DQM /CS
10
D0
DQMB4 8 DQ32 to DQ39
DQM
I/O0 to I/O7 /CS DQM
10
D5
I/O0 to I/O7 /CS DQM
DQMB1 8 DQ8 to DQ15
10
D1
DQMB5 8 DQ40 to DQ47
I/O0 to I/O7 /CS DQM
10
D6
I/O0 to I/O7
8 CB0 to CB7
10
D2
I/O0 to I/O7
/S2 /CS DQMB2 8 DQ16 to DQ23 DQM /CS
10
D3
DQMB6 8 DQ48 to DQ55
DQM
I/O0 to I/O7 /CS DQM
10
D7
I/O0 to I/O7 /CS DQM
DQMB3 8 DQ24 to DQ31
10
D4
DQMB7 8 DQ56 to DQ63
I/O0 to I/O7
10
D8
I/O0 to I/O7
VCC
10
CK0 CLK ; 5 SDRAMs VSS
0.33F x 9 pcs
VCC (D0 to D8, U0) 0.1F x 9 pcs VSS (D0 to D8, U0) Serial PD
10
CK1 10 pF SCL SCL SDA SDA
10
CK2 CLK; 4 SDRAMs + 3.3 pF cap
U0
WP A0 10 pF A1 A2 47k
10
CK3
SA0 SA1 SA2 VSS Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D8: HM5225805 U0: 2k bits EEPROM
CKE0
CKE (D0 to D8)
Data Sheet E0184H10 (Ver. 1.0)
10
HB52F328EM-75B, HB52F329EM-75B
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation (HB52F328EM) Power dissipation (HB52F329EM) Operating temperature Storage temperature Symbol VT VCC IOUT PT PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 (max.)) -0.5 to +4.6 50 8.0 9.0 0 to +65 -55 to +125 Unit V V mA W W C C Note 1 1
Notes: 1. Respect to VSS. DC Operating Conditions (TA = 0 to +65C)
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage VIH VIL min. 3.0 0 2.0 -0.3 max. 3.6 0 VCC + 0.3 0.8 Unit V V V V Note 1, 2 3 1, 4 1, 5
Notes: 1. 2. 3. 4. 5.
All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max.) = VCC + 2.0V for pulse width 3ns at VCC. VIL (min.) = VSS - 2.0V for pulse width 3ns at VSS.
Data Sheet E0184H10 (Ver. 1.0)
11
HB52F328EM-75B, HB52F329EM-75B
DC Characteristics (TA = 0 to 65C, VCC = 3.3V 0.3V, VSS = 0V)
Parameter /CE latency Operating current (CL = 2) (CL = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current (CL = 2) (CL = 3) Refresh current Self refresh current Symbol ICC1 ICC1 ICC2P ICC2PS ICC2N ICC3P ICC3N ICC4 ICC4 ICC5 ICC6 PC100 PC133 Grade PC100 PC133 HB52F328EM max. 880 880 24 16 160 32 240 800 1080 1760 24 HB52F329EM max. 990 990 27 18 180 36 270 900 1215 1980 27 Unit mA mA mA mA mA mA mA mA mA mA mA tRC = min. VIH VCC - 0.2 V VIL 0.2 V 3 8 CKE = VIL, tCK = 12ns 6 CKE = VIL, tCK = CKE, /S = VIH, tCK = 12ns 7 4 Test condition Burst length = 1 tRC = min. Notes 1, 2, 3
CKE = VIL, tCK = 12ns 1, 2, 6 CKE, /S = VIH, tCK = 12ns tCK = min., BL = 4 1, 2, 4 1, 2, 5
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK operating current. 7. After power down mode, no CK operating current. 8. After self refresh mode set, self refresh current. DC Characteristics2 (TA = 0 to 65C, VCC = 3.3V 0.3V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL min. -10 -10 2.4 -- max. 10 10 -- 0.4 Unit A A V V Test condition 0 VIN VCC 0 VOUT VCC DQ = disable IOH = -4mA IOL = 4mA Notes
Data Sheet E0184H10 (Ver. 1.0)
12
HB52F328EM-75B, HB52F329EM-75B
Pin Capacitance (TA = 25C, VCC = 3.3V 0.3V) (HB52F328EM)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 CI5 CI6 Input/Output capacitance CI/O1 Pin Address /RE, /CE, /W CKE /S CK DQMB DQ max. 70 63 68 34 50 16 14 Unit pF pF pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Pin Capacitance (TA = 25C, VCC = 3.3V 0.3V) (HB52F329EM)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 CI5 CI6 Input/Output capacitance CI/O1 Pin Address /RE, /CE, /W CKE /S CK DQMB DQ max. 72 66 70 39 50 21 14 Unit pF pF pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Notes: 1.Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. Measurement condition: f = 1MHz, 1.4Vbias, 200mV swing. 3. DQMB = VIH to disable Data-out. 4. This parameter is sampled and not 100% tested.
Data Sheet E0184H10 (Ver. 1.0)
13
HB52F328EM-75B, HB52F329EM-75B
AC Characteristics (TA = 0 to 65C,VCC = 3.3V 0.3V, VSS = 0V)
PC133 CL = 3 Parameter System clock cycle time CK high pulse width CK low pulse width Access time from CK Data-out hold time CK to Data-out low impedance CK to Data-out high impedance Data-in setup time Data in hold time Address setup time Address hold time CKE setup time CKE setup time for power down exit CKE hold time Command setup time Command hold time Ref/Active to Ref/Active command period Active to precharge command period Active command to column command (same bank) Precharge to active command period Symbol tCK tCKH tCKL tAC tOH tLZ tHZ tDS tDH tAS tAH tCES tCESP tCEH tCS tCH tRC tRAS tRCD tRP Tsi Thi Tsi Thi Tsi Tpde Thi Tsi Thi Trc Tras Trcd Trp Tdpl Trrd PC100 Symbol Tclk Tch Tcl Tac Toh min. 7.5 2.5 2.5 -- 2.7 2 -- 1.5 0.8 1.5 0.8 1.5 1.5 0.8 1.5 0.8 67.5 45 20 20 15 15 1 -- max. -- -- -- 5.4 -- -- 5.4 -- -- -- -- -- -- -- -- -- -- 120000 -- -- -- -- 5 64 PC100 CL = 2 min. 10 3 3 -- 3 2 -- 2 1 2 1 2 2 1 2 1 70 50 20 20 20 20 1 -- max. -- -- -- 6 -- -- 6 -- -- -- -- -- -- -- -- -- -- 120000 -- -- -- -- 5 64 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Notes 1 1 1 1, 2 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 1 1 1 1 1 1 1 1
Write recovery or data-in to precharge lead tDPL time Active (a) to Active (b) command period Transition time (rise and fall) Refresh period tRRD tT tREF
Notes: 1. 2. 3. 4. 5.
AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.5V. Access time is measured at 1.5V. Load condition is CL = 50pF. tLZ (min.) defines the time at which the outputs achieves the low impedance state. tHZ (max.) defines the time at which the outputs achieves the high impedance state. tCES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions * Input and output timing reference levels: 1.5V * Input waveform and output load: See following figures
2.4V
input
0.4V
2.0V 0.8V
I/O CL tT
tT
Output load
Data Sheet E0184H10 (Ver. 1.0)
14
HB52F328EM-75B, HB52F329EM-75B
Relationship Between Frequency and Minimum Latency
Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance Last data out to active command (Auto precharge, same bank) Last data out to precharge (early precharge) Column command to column command Write command to data in latency DQMB to data in DQMB to data out CKE to CK disable Register set to active command /S to command disable Power down exit to command input Symbol IRCD IRC IRAS IRP IDPL IRRD ISREX IAPW ISEC IHZP IAPR IEP ICCD IWCD IDID IDOD ICLE IRSA ICDD IPEC Tccd Tdwd Tdqm Tdqz Tcke Tmrd Troh Tsrx Tdal Tdpl PC100 Symbol CL = 3 133 7.5 3 9 6 3 2 2 1 5 9 3 1 -2 1 0 0 2 1 1 0 1 CL = 2 100 10 2 7 5 2 2 2 1 4 7 2 1 -1 1 0 0 2 1 1 0 1 Notes 1 = [IRAS + IRP] 1 1 1 1 1 2 = [IDPL + IRP] = [IRC] 3
Notes: 1. IRCD to IRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]
Data Sheet E0184H10 (Ver. 1.0)
15
HB52F328EM-75B, HB52F329EM-75B
Pin Functions
CK0, CK2 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. /S0, /S2 (input pin): When /S is Low, the command input cycle becomes valid. When /S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RE, /CE and /W (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0, BA1 (BA) is precharged. BA0, BA1 (input pin): BA0, BA1 are bank select signal (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 is Low and BA0 is Low, bank 0 is selected. If BA1 is High and BA0 is Low, bank 1 is selected. If BA1 is Low and BA0 is High, bank 2 is selected. If BA1 is High and BA0 is High, bank 3 is selected. CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins. VCC (power supply pins): 3.3V is applied. VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet (E0082H).
Data Sheet E0184H10 (Ver. 1.0)
16
HB52F328EM-75B, HB52F329EM-75B
Physical Outline
Front side 133.37 0.15 5.251 0.006 (DATUM -A-) 4.00 max 0.157 max Unit: mm inch
3.00 typ 0.118 typ (63.67) (2.51)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Front) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 1 84 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
C 11.43 0.450 36.83 1.450 B 54.61 2.150 A
; ; ; ; ; ; ;
3.00 0.10 0.118 0.004
1.27 0.10 0.050 0.004
Back side 4.00 0.10 0.157 0.004 2 - 3.00 0.10 2 - 0.118 0.003 85
127.35 0.15 5.014 0.006
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Component area ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (Back) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (DATUM -A-)
Detail A 2.50 0.20 0.098 0.008 0.20 0.15 0.010 0.0004 1.27 0.050 Detail B R FULL (DATUM -A-) Detail C 1.00 0.039 168
17.80 0.70
R FULL
3.125 0.125 0.123 0.005
1.00 0.05 0.039 0.002
Note: Tolerance on all dimensions 0.15/0.006 unless otherwise specified.
Data Sheet E0184H10 (Ver. 1.0)
17
3.125 0.125 0.123 0.005
6.35 0.250 2.00 0.10 0.079 0.004
6.35 0.250 4.175 0.164 2.00 0.10 0.079 0.004
34.925 1.375
4.00 min 0.157 min
HB52F328EM-75B, HB52F329EM-75B
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet E0184H10 (Ver. 1.0)
18
HB52F328EM-75B, HB52F329EM-75B
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M02 01. 4
Data Sheet E0184H10 (Ver. 1.0)
19

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